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LC2MOS Quad 8-Bit D/A Converter AD7226
FEATURES Four 8-Bit DACs with Output Amplifiers Skinny 20-Lead DIP, SOIC, SSOP, and PLCC Packages Microprocessor-Compatible TTL/CMOS-Compatible No User Trims Extended Temperature Range Operation Single Supply Operation Possible APPLICATIONS Process Control Automatic Test Equipment Automatic Calibration of Large System Parameters, e.g., Gain/Offset
MSB DATA (8-BIT) LSB
FUNCTIONAL BLOCK DIAGRAM
VREF VDD
LATCH A
DAC A
A
VOUTA
D A T A B U S
LATCH B
DAC B
B
VOUTB
LATCH C
DAC C
C
VOUTC
LATCH D WR A1 A0 CONTROL LOGIC
DAC D
D
VOUTD
AD7226
VSS
AGND
AGND
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7226 contains four 8-bit voltage-output digital-toanalog converters, with output buffer amplifiers and interface logic on a single monolithic chip. No external trims are required to achieve full specified performance for the part. Separate on-chip latches are provided for each of the four D/A converters. Data is transferred into one of these data latches through a common 8-bit TTL/CMOS (5 V) compatible input port. Control inputs A0 and A1 determine which DAC is loaded when WR goes low. The control logic is speed-compatible with most 8-bit microprocessors. Each D/A converter includes an output buffer amplifier capable of driving up to 5 mA of output current. The amplifiers' offsets are laser-trimmed during manufacture, thereby eliminating any requirement for offset nulling. Specified performance is guaranteed for input reference voltages from 2 V to 12.5 V with dual supplies. The part is also specified for single supply operation at a reference of 10 V. The AD7226 is fabricated in an all ion-implanted high speed Linear Compatible CMOS (LC2MOS) process, which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip.
1. DAC-to-DAC Matching Since all four DACs are fabricated on the same chip at the same time, precise matching and tracking between the DACs is inherent. 2. Single-Supply Operation The voltage mode configuration of the DACs allows the AD7226 to be operated from a single power supply rail. 3. Microprocessor Compatibility The AD7226 has a common 8-bit data bus with individual DAC latches, providing a versatile control architecture for simple interface to microprocessors. All latch enable signals are level triggered. 4. Small Size Combining four DACs and four op amps plus interface logic into a 20-pin package allows a dramatic reduction in board space requirements and offers increased reliability in systems using multiple converters. Its pinout is aimed at optimizing board layout with all the analog inputs and outputs at one end of the package and all the digital inputs at the other.
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD7226-SPECIFICATIONS
DUAL SUPPLY
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Temperature Coefficient Zero Code Error Zero Code Error Temperature Coefficient REFERENCE INPUT Voltage Range Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Digital Crosstalk Minimum Load Resistance POWER SUPPLIES VDD Range IDD ISS SWITCHING CHARACTERISTICS4, 5 Address to Write Setup Time, tAS Address to Write Hold Time, tAH Data Valid to Write Setup Time, tDS Data Valid to Write Hold Time, tDH Write Pulsewidth, tWR
(VDD = 11.4 V to 16.5 V, VSS = -5 V 10%, AGND = DGND = 0 V; VREF = +2 V to (VDD - 4 V)1, unless otherwise noted. All Specifications TMIN to TMAX unless otherwise noted.)
K, B Versions2 8 1 0.5 1 0.5 20 20 50 2 to (VDD - 4) 2 50 200 2.4 0.8 1 8 Binary 2.5 4 10 2 11.4/16.5 13 11 0 0 50 0 50
Unit Bits LSB max LSB max LSB max LSB max ppm/C typ mV max mV/C typ V min to V max kW min pF min pF max V min V max mA max pF max
Conditions/Comments
VDD = 15 V 5%, VREF = 10 V Guaranteed Monotonic VDD = 14 V to 16.5 V, VREF = +10 V
Occurs when each DAC is loaded with all 0s. Occurs when each DAC is loaded with all 1s.
VIN = 0 V or VDD
V/ms min ms max nV secs typ kW min V min/V max mA max mA max ns min ns min ns min ns min ns min
VREF = 10 V; Settling Time to 1/2 LSB VOUT = 10 V For Specified Performance Outputs Unloaded; VIN = VINL or VINH Outputs Unloaded; VIN = VINL or VINH
NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K Version: -40C to +85C B Version: -40C to +85C 3 Guaranteed by design. Not production tested. 4 Sample Tested at 25C to ensure compliance. 5 Switching Characteristics apply for single and dual supply operation. Specifications subject to change without notice.
-2-
REV. C
AD7226 SINGLE SUPPLY
Parameter STATIC PERFORMANCE Resolution Total Unadjusted Error Differential Nonlinearity REFERENCE INPUT Input Resistance Input Capacitance3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current Input Capacitance Input Coding DYNAMIC PERFORMANCE Voltage Output Slew Rate4 Voltage Output Settling Time4 Digital Crosstalk Minimum Load Resistance POWER SUPPLIES VDD Range IDD
NOTES 1 Maximum possible reference voltage. 2 Temperature ranges are as follows: K Version: -40C to +85C B Version: -40C to +85C 3 Guaranteed by design. Not production tested. 4 Sample Tested at 25C to ensure compliance. Specifications subject to change without notice.
(VDD = 15 V 5%, VSS = AGND = DGND = O V; VREF = 10 V unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
K, B Versions2 8 2 1 2 50 200 2.4 0.8 1 8 Binary 2 4 10 2 14.25/15.75 13 Unit Bits LSB max LSB max kW min pF min pF max V min V max mA max pF max Conditions/Comments
1
Guaranteed Monotonic
Occurs when each DAC is loaded with all 0s. Occurs when each DAC is loaded with all 1s.
VIN = 0 V or VDD
V/ms min ms max nV secs typ kW min V min/V max mA max
Settling Time to 1/2 LSB VOUT = +10 V For Specified Performance Outputs Unloaded; VIN = VINL or VINH
ABSOLUTE MAXIMUM RATINGS 1
ORDERING GUIDE Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Total1 Unadjusted Error 1 LSB 1 LSB 1 LSB 1 LSB 1 LSB Package Option2 N-20 P-20A RW-20 Q-20 RS-20
Model AD7226KN AD7226KP AD7226KR AD7226BQ AD7226BRS
NOTES 1 Dual-Supply Operation 2 N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = CERDIP; RW = SOIC; RS = SSOP
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V, VDD VSS to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -7 V, VDD VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +24 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD Digital Input Voltage to DGND . . . . . . . -0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, VDD VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD Power Dissipation (Any Package) to 75C . . . . . . . . . . 500 mW Derates above 75C by . . . . . . . . . . . . . . . . . . . . . 2.0 mW/C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . . -40C to +85C Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Outputs may be shorted to AGND provided that the power dissipation of the package is not exceeded. Typically short circuit current to AGND is 50 mA.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7226 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. C
-3-
AD7226
PIN CONFIGURATIONS DIP and SOIC/SSOP
VOUTB 1 VOUTA 2 VSS 3 VREF 4 AGND 5 DGND 6 VOUTC VOUTD VDD A0 A1
20 19 18 17
AD7226
16
TOP VIEW 15 WR (Not to Scale) 14 DB0(LSB) DB7 (MSB) 7 DB6 8 DB5 9 DB4 10
13 12 11
DB1 DB2 DB3
PLCC
VOUTB
1
VOUTC
20
3
2
VOUTD
19
18 VDD 17 A0 16 A1 15 WR 14 DB0(LSB) 13
V REF 4 AGND 5 DGND 6 DB7 (MSB) 7 DB8 8
9 10 11 12
TOP VIEW (Not to Scale)
DB5
DB4
VOUTA
VSS
AD7226
DB3
DB2
TERMINOLOGY TOTAL UNADJUSTED ERROR
DIFFERENTIAL NONLINEARITY
This is a comprehensive specification that includes full-scale error, relative accuracy and zero code error. Maximum output voltage is VREF - 1 LSB (ideal), where 1 LSB (ideal) is VREF/ 256. The LSB size will vary over the VREF range. Hence the zero code error will, relative to the LSB size, increase as VREF decreases. Accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of LSB's over the VREF range. As a result, total unadjusted error is specified for a fixed reference voltage of 10 V.
RELATIVE ACCURACY
Differential Nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity.
DIGITAL CROSSTALK
The glitch impulse transferred to the output of one converter due to a change in the digital input code to another of the converters. It is specified in nV secs and is measured at VREF = 0 V.
FULL SCALE ERROR
Full-Scale Error is defined as: Measured Value - Zero Code Error - Ideal Value
Relative Accuracy or endpoint nonlinearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after allowing for zero and full-scale error and is normally expressed in LSB's or as a percentage of full-scale reading.
-4-
DB1
REV. C
AD7226
CIRCUIT INFORMATION D/A SECTION
In single supply operation (VSS = 0 V = AGND), with the output approaching AGND (i.e., digital code approaching all 0s)
VDD
The AD7226 contains four identical, 8-bit, voltage mode digital-toanalog converters. The output voltages from the converters have the same polarity as the reference voltage allowing single supply operation. A novel DAC switch pair arrangement on the AD7226 allows a reference voltage range from 2 V to 12.5 V. Each DAC consists of a highly stable, thin-film, R-2R ladder and eight high speed NMOS, single-pole, double-throw switches. The simplified circuit diagram for one channel is shown in Figure 1. Note that VREF (Pin 4) and AGND (Pin 5) are common to all four DACs.
I/P
O/P 400 A
VSS
Figure 2. Amplifier Output Stage
R 2R 2R DB0 VREF AGND SHOWN FOR ALL 1s ON DAC 2R DB5 R 2R DB6 R 2R DB7 VOUT
the current load ceases to act as a current sink and begins to act as a resistive load of approximately 2 kW to AGND. This occurs as the NMOS transistors come out of saturation. This means that, in single supply operation, the sink capability of the amplifiers is reduced when the output voltage is at or near AGND. A typical plot of the variation of current sink capability with output voltage is shown in Figure 3.
500
Figure 1. D/A Simplified Circuit Diagram
The input impedance at the VREF pin of the AD7226 is the parallel combination of the four individual DAC reference input impedances. It is code dependent and can vary from 2 kW to infinity. The lowest input impedance (i.e., 2 KW) occurs when all four DACs are loaded with the digital code 01010101. Therefore, it is important that the reference presents a low output impedance under changing load conditions. The nodal capacitance at the reference terminals is also code dependent and typically varies from 100 pF to 250 pF. Each VOUT pin can be considered as a digitally programmable voltage source with an output voltage of:
VOUTX = DX V REF
VSS = -5V 400
ISINK ( A)
300 VSS = 0 200 VDD = +15V
100
(1)
0
0
2
4 VOUT (V)
6
8
10
where DX is fractional representation of the digital input code and can vary from 0 to 255/256. The source impedance is the output resistance of the buffer amplifier.
OP AMP SECTION
Figure 3. Variation of ISINK with VOUT
Each voltage-mode D/A converter output is buffered by a unity gain, noninverting CMOS amplifier. This buffer amplifier is capable of developing 10 V across a 2 kW load and can drive capacitive loads of 3300 pF. The output stage of this amplifier consists of a bipolar transistor from the VDD line and a current load to the VSS, the negative supply for the output amplifiers. This output stage is shown in Figure 2. The NPN transistor supplies the required output current drive (up to 5 mA). The current load consists of NMOS transistors which normally act as a constant current sink of 400 mA to VSS, giving each output a current sink capability of approximately 400 mA if required. The AD7226 can be operated single or dual supply resulting in different performance in some parameters from the output amplifiers.
If the full sink capability is required with output voltages at or near AGND (= 0 V), then VSS can be brought below 0 V by 5 V and thereby maintain the 400 mA current sink as indicated in Figure 3. Biasing VSS below 0 V also gives additional headroom in the output amplifier which allows for better zero code error performance on each output. Also improved is the slew rate and negative-going settling time of the amplifiers (discussed later). Each amplifier offset is laser trimmed during manufacture to eliminate any requirement for offset nulling.
DIGITAL SECTION
The digital inputs of the AD7226 are both TTL and CMOS (5 V) compatible from VDD = 11.4 V to 16.5 V. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Internal input protection is achieved by an on-chip distributed diode from DGND to each MOS gate. To minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (VDD and DGND) as practically possible.
REV. C
-5-
AD7226
INTERFACE LOGIC INFORMATION
Address lines A0 and A1 select which DAC will accept data from the input port. Table I shows the selection table for the four DACs with Figure 4 showing the input control logic. When the WR signal is LOW, the input latches of the selected DAC are transparent and its output responds to activity on the data bus. The data is latched into the addressed DAC latch on the rising edge of WR. While WR is high the analog outputs remain at the value corresponding to the data held in their respective latches.
Table I. AD7226 Truth Table
A0
TO LATCH A
A1
TO LATCH B
TO LATCH C
WR
TO LATCH D
AD7226 Control Inputs WR A1 A0 H L L L L X L L L L H H H H X L L H H L L H H
AD7226 Operation No Operation Device Not Selected DAC A Transparent DAC A Latched DAC B Transparent DAC B Latched DAC C Transparent DAC C Latched DAC D Transparent DAC D Latched
Figure 4. Input Control Logic
tDS
DATA VINH VINL
tDH
VDD 0
tAS
ADDRESS VINH VINL
tAH
VDD 0
WR
tWR
VDD 0
L = Low State, H = High State, X = Don't Care
NOTES 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. tr = tf = 20ns OVER VDD RANGE. 2. TIMING MEASUREMENT REFERENCE LEVEL IS VINH + VINL
2
3. SELECTED INPUT LATCH IS TRANSPARENT WHILE WR IS LOW, THUS INVALID DATA DURING THIS TIME CAN CAUSE SPURIOUS OUTPUTS.
Figure 5. Write Cycle Timing Diagram
-6-
REV. C
Typical Performance Characteristics-AD7226
(TA = 25 C, VDD = 15 V, VSS = -5 V)
AD7226K, B
2.0
4
VREF = 10V 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0
DIFFERENTIAL NONLINEARITY (LSBs)
TOTAL UNADJUSTED ERROR (LSBs)
1.5
3 2 1 0 -1 -2 -3 -4 0 2 4 6 8 VREF (V) 10 12 14
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 INPUT CODE (DECIMAL EQUIVALENT)
TPC 1. Channel-to-Channel Matching
TPC 3. Differential Nonlinearity vs. VREF
4 3
AD7226K, B
2.0 1.5
RELATIVE ACCURACY (LSBs)
2 1 0 -1 -2 -3 -4 0 2 4 6 8 VREF (V) 10 12 14
ZERO CODE ERROR (LSBs)
1.0 0.5 VOUT A 0 -0.5 -1.0 -1.5 -2.0 VOUTD VOUTB VOUTC
0
10
20
30
40
50 60 70 80 90 100 110 120 130 TEMPERATURE ( C)
TPC 2. Relative Accuracy vs. VREF
TPC 4. Zero Code Error vs. Temperature
REV. C
-7-
AD7226
SPECIFICATION RANGES
In order for the DACs to operate to their specifications, the reference voltage must be at least 4 V below the VDD power supply voltage. This voltage differential is required for correct generation of bias voltages for the DAC switches. The AD7226 is specified to operate over a VDD range from +12 V 5% to +15 V 10% (i.e., from +11.4 V to +16.5 V) with a VSS of -5 V 10%. Operation is also specified for a single +15 V 5% VDD supply. Applying a VSS of -5 V results in improved zero code error, improved output sink capability with outputs near AGND and improved negative-going settling time. Performance is specified over a wide range of reference voltages from 2 V to (VDD - 4 V) with dual supplies. This allows a range of standard reference generators to be used such as the AD780, a 2.5 V band gap reference and the AD584, a precision 10 V reference. Note that in order to achieve an output voltage range of 0 V to 10 V a nominal 15 V 5% power supply voltage is required by the AD7226.
SETTLING TIME
DATA
+1/2 LSB O/P -1/2 LSB
Figure 7a. Positive Step Settling Time (VSS = -5 V)
DATA
The output stage of the buffer amplifiers consists of a bipolar NPN transistor from the VDD line and a constant current load to VSS. VSS is the negative power supply for the output buffer amplifiers. As mentioned in the op amp section, in single supply operation the NMOS transistor will come out of saturation as the output voltage approaches AGND and will act as a resistive load of approximately 2 kW to AGND. As a result, the settling time for negative-going signals approaching AGND in single supply operation will be longer than for dual supply operation where the current load of 400 mA is maintained all the way down to AGND. Positive-going settling-time is not affected by VSS. The settling-time for the AD7226 is limited by the slew-rate of the output buffer amplifiers. This can be seen from Figure 6 which shows the dynamic response for the AD7226 for a full scale change. Figures 7a and 7b show expanded settling-time photographs with the output waveforms derived from a differential input to an oscilloscope. Figure 7a shows the settling time for a positive-going step and Figure 7b shows the settling time for a negative-going output step.
+1/2 LSB
O/P -1/2 LSB
Figure 7b. Negative Step Settling Time (VSS = -5 V)
GROUND MANAGEMENT
AC or transient voltages between AGND and DGND can cause noise at the analog output. This is especially true in microprocessor systems where digital noise is prevalent. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7226. In more complex systems where the AGND and DGND intertie is on the backplane, it is recommended that two diodes be connected in inverse parallel between the AD7226 AGND and DGND pins (IN914 or equivalent).
Unipolar Output Operation
DATA
VOUT
This is the basic mode of operation for each channel of the AD7226, with the output voltage having the same positive polarity as +VREF. The AD7226 can be operated single supply (VSS = AGND) or with positive/negative supplies (see op amp section which outlines the advantages of having negative VSS). The code table for unipolar output operation is shown in Table II. Note that the voltage at VREF must never be negative with respect to DGND in order to prevent parasitic transistor turn-on. Connections for the unipolar output operation are shown in Figure 8.
Figure 6. Dynamic Response (VSS = -5 V)
-8-
REV. C
AD7226
VREF VDD
With R1 = R2
MSB
DB7
VOUT = (2D A - 1) V REF
(4)
VOUTA
where DA is a fractional representation of the digital word in latch A. Mismatch between R1 and R2 causes gain and offset errors and therefore these resistors must match and track over temperature. Once again the AD7226 can be operated in single supply or from positive/negative supplies. Table III shows the digital code versus output voltage relationship for the circuit of Figure 9 with R1 = R2.
VREF R1
DAC A
DB0
VOUTB
LSB
DAC B
WR
VOUTC
DAC C
A1 A0
VOUTD
VREF
VDD
R2 +15V
DAC D
AD7226*
VOUTA
VOUT -15V
VSS AGND
DGND
DAC A
R1, R2 = 10k
0.1%
Figure 8. AD7226 Unipolar Output Circuit
VSS AGND DGND
*DIGITAL INPUTS OMITTED FOR CLARITY
Table II. Unipolar Code Table
Figure 9. AD7226 Bipolar Output Circuit
DAC Latch Contents MSB LSB 1111 1111
Analog Output E 255 +V REF A E 256 E 129 +V REF A E 256 E 128 V REF +V REF A =+ E 256 2 E 127 +V REF A E 256 E1 +V REF A E 256 0V (2)
Table III. Bipolar (Offset Binary) Code Table
DAC Latch Contents MSB LSB 1111 1000 1000 0111 0000 0000
AGND BIAS
Analog Output E 127 +V REF A E 128 E1 +V REF A E 128 0V E1 -V REF A E 128 E 127 -V REF A E 128 E 128 -V REF A = -V REF E 128
1000
0001
1111 0001 0000 1111 0001 0000
1000
0000
0111
1111
0000
0001
0000
0000
E1 Note: LSB = (VREF ) 2-8 = VREF A E 256
()
Bipolar Output Operation
Each of the DACs of the AD7226 can be individually configured to provide bipolar output operation. This is possible using one external amplifier and two resistors per channel. Figure 9 shows a circuit used to implement offset binary coding (bipolar operation) with DAC A of the AD7226. In this case
E R2 E R2 VOUT = A1 + ( DAVREF ) - A (VREF ) R1 E R1 E
The AD7226 AGND pin can be biased above system GND (AD7226 DGND) to provide an offset "zero" analog output voltage level. Figure 10 shows a circuit configuration to achieve this for channel A of the AD7226. The output voltage, VOUTA, can be expressed as: VOUT A = VBIAS + DA (VIN ) (5) where DA is a fractional representation of the digital input word (0 D 255/256).
(3)
REV. C
-9-
AD7226
VREF VDD
AD7226*
VOUTA DAC A
AGND
5
VBIAS
VSS
DGND
generated in software with each D/A converter being loaded from a separate loop. The loops run through the look-up table producing successive triads of sinusoidal values with 120 separation which are loaded to the D/A converters producing three sine wave voltages 120 apart. A complete sine wave cycle is generated by stepping through the full look-up table. If a 256-element sine wave table is used then the resolution of the circuit will be 1.4 (360/256). Figure 13 shows typical resulting waveforms. The sine waves can be smoothed by filtering the D/A converter outputs. The fourth D/A converter of the AD7226, DAC D, may be used in a feedback configuration to provide a programmable reference voltage for itself and the other three converters. This configuration is shown in Figure 11. The relationship of VREF to VIN is dependent upon digital code and upon the ratio of RF to R and is given by the formula.
*DIGITAL INPUTS OMITTED FOR CLARITY
Figure 10. AGND Bias Circuit
For a given VIN, increasing AGND above system GND will reduce the effective VDD-VREF which must be at least 4 V to ensure specified operation. Note that because the AGND pin is common to all four DACs, this method biases up the output voltages of all the DACs in the AD7226. Note that VDD and VSS of the AD7226 should be referenced to DGND.
3-PHASE SINE WAVE
V REF =
(1 + G DD )
(1 + G )
V IN
(6)
where G = RF/R and DD is a fractional representation of the digital word in latch D. Alternatively, for a given VIN and resistance ratio, the required value of DD for a given value of VREF can be determined from the expression V R DD = (1 + R / R F ) IN - (7) V REF R F Figure 12 shows typical plots of VREF versus digital code for three different values of RF. With VIN = 2.5 V and RF = 3 R the peak-to-peak sine wave voltage from the converter outputs will vary between 2.5 V and 10 V over the digital input code range of 0 to 255.
VIN VREF A0 A1 WR VOUTA VOUTB RF VOUTC VOUTD R
The circuit of Figure 11 shows an application of the AD7226 in the generation of 3-phase sine waves which can be used to control small 3-phase motors. The proper codes for synthesizing a full sine wave are stored in EPROM, with the required phaseshift of 120 between the three D/A converter outputs being generated in software. Data is loaded into the three D/A converters from the sine EPROM via the microprocessor or control logic. Three loops are
ADDRESS BUS
MICROPROCESSOR OR CONTROL LOGIC
SINE EPROM
ADDRESS DECODE
AD7226
DATA BUS
Figure 11. 3-Phase Sine Wave Generation Circuit
4.0 V IN
VDD = +15 V VSS = -5 V
3.5 V IN
RF = 3R
VOUTA
3.0 V IN
VREF
2.5 V IN RF = 2R
VOUTB
2.0 V IN
VOUTC
1.5 V IN
RF = R
VIN
0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 DIGITAL CODE (Decimal Equivalent)
Figure 12. Variation of VREF with Feedback Configuration
Figure 13. 3-Phase Sine Wave Output
-10-
REV. C
AD7226
STAIRCASE WINDOW COMPARATOR
In many test systems, it is important to be able to determine whether some parameter lies within defined limits. The staircase window comparator of Figure 14a is a circuit that can be used, for example, to measure the VOH and VOL thresholds of a TTL device under test. Upper and lower limits on both VOH and VOL can be programmably set using the AD7226. Each adjacent pair of comparators forms a window of programmable size. If VTEST lies within a window, then the output for that window will be high. With a reference of 2.56 V applied to the VREF input, the minimum window size is 10 mV.
VTEST FROM D.U.T. 1/4 CA339 10k VREF VDD VOH (HIGH) VOUTA 5V 10k WINDOW 2 5V WINDOW 1
VTEST FROM D.U.T.
10k VREF VOUTA VOUTB VDD 5V WINDOW 1
AD7226
VOUTC VOUTD AGND
5V
10k
WINDOW 2
5V
10k
WINDOW 3
Figure 15a. Overlapping Windows
VREF WINDOW 1 VOUTB VOUTA WINDOW 2 VOUTD
VOH (LOW) VOUTB 10k
AD7226
VOL (HIGH) VOUTC
5V
WINDOW 3
VOUTC AGND
WINDOW 3
Figure 15b. Window Structure
5V 10k WINDOW 4
+15V +4V
VOUTD AGND
VOL (LOW) 10k 5V
-4V
15k 10k VREF *DIGITAL INPUTS OMITTED FOR CLARITY VDD
WINDOW 5
AD7226*
VOUTA DAC A
Figure 14a. Logic Level Measurement
VREF WINDOW 1 VOUTA VOUTB WINDOW 2
VSS
AGND
DGND
WINDOW 3 VOUTC WINDOW 4 VOUTD WINDOW 5 AGND
Figure 16. Varying Reference Signal
VARYING REFERENCE SIGNAL
Figure 14b. Window Structure
The circuit can easily be adapted to allow for overlapping of windows as shown in Figure 15a. If the three outputs from this circuit are decoded then five different nonoverlapping programmable windows can again be defined.
In some applications, it may be desirable to have a varying signal applied to the reference input of the AD7226. The AD7226 has multiplying capability within upper and lower limits of reference voltage when operated with dual supplies. The upper and lower limits are those required by the AD7226 to achieve its linearity specification. Figure 16 shows a sine wave signal applied to the reference input of the AD7226. For input signal frequencies up to 50 kHz, the output distortion typically remains less than 0.1%. Typical 3 dB bandwidth figure is 700 kHz.
REV. C
-11-
AD7226
OFFSET ADJUST
+10V
Figure 17 shows how the AD7226 can be used to provide programmable input offset voltage adjustment for the AD544 op amp. Each output of the AD7226 can be used to trim the input offset voltage on one AD544. The 620 kW resistor tied to 10 V provides a fixed bias current to one offset node. For symmetrical adjustment, this bias current should equal the current in the other offset node with the half-full scale code (i.e., 10000000) on the DAC. Changing the code on the DAC varies the bias current and hence provides offset adjust for the AD544. For example, the input offset voltage on the AD544J, which has a maximum of 2 mV, can be programmably trimmed to 10 mV.
VREF
VDD
+15V
AD7226*
VOUTA DAC A 500k 1
7 5 620k
4
VSS
AGND
DGND -15V *DIGITAL INPUTS OMITTED FOR CLARITY
Figure 17. Offset Adjust for AD544
8085A A15 ADDRESS BUS A8 WR ADDRESS EN DECODE
6502
A15 ADDRESS BUS A0
AD7226*
WR A0 A1 DB7
R/W 2
EN ADDRESS EN DECODE
A0 A1 WR
AD7226*
DB7 DB0 D7
ALE D7
DS2 8212
DB0
ADDRESS/DATA BUS D0 *LINEAR CIRCUITRY OMITTED FOR CLARITY
D0
DATA BUS *LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 18. AD7226 to 8085A Interface
6809 A15 ADDRESS BUS A0 R/W EN ADDRESS EN DECODE A0 A1 WR Z-80
Figure 20. AD7226 to 6502 Interface
A15 ADDRESS BUS A0 WR ADDRESS EN DECODE A0 A1 WR
E
AD7226*
DB7 DB0
AD7226*
DB7 DB0 D7
D7 DATA BUS D0 *LINEAR CIRCUITRY OMITTED FOR CLARITY
DATA BUS D0 *LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 19. AD7226 to 6809 Interface
Figure 21. AD7226 to Z-80 Interface
-12-
REV. C
AD7226
OUTLINE DIMENSIONS 20-Lead Plastic Dual In-Line Package [PDIP] (N-20)
Dimensions shown in inches and (millimeters)
0.985 (25.02) 0.965 (24.51) 0.945 (24.00)
20 1 11 10
0.295 (7.49) 0.285 (7.24) 0.275 (6.99) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62)
0.180 (4.57) MAX
0.015 (0.38) MIN
0.150 (3.81) 0.135 (3.43) 0.120 (3.05)
0.150 (3.81) 0.130 (3.30) 0.110 (2.79)
0.022 (0.56) 0.018 (0.46) 0.014 (0.36)
0.100 0.060 (1.52) SEATING (2.54) 0.050 (1.27) PLANE BSC 0.045 (1.14)
0.015 (0.38) 0.010 (0.25) 0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MO-095-AE CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
20-Lead Ceramic Dual In-Line Package [CERDIP] (Q-20)
Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN PIN 1
1 10
0.098 (2.49) MAX
20 11
0.310 (7.87) 0.220 (5.59)
0.200 (5.08) MAX
1.060 (26.92) MAX
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)
0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.100 (2.54) BSC
0.070 (1.78) SEATING 0.030 (0.76) PLANE
15 0
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
20-Lead Shrink Small Outline Package [SSOP] (RS-20)
Dimensions shown in millimeters
7.50 7.20 6.90
20
11
8.20 7.80 7.40
1 10
5.60 5.30 5.00
2.00 MAX
1.85 1.75 1.65
0.25 0.09 8 4 0 0.95 0.75 0.55
0.05 MIN COPLANARITY 0.10
0.65 BSC
0.38 0.22
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AE
REV. C
-13-
AD7226
OUTLINE DIMENSIONS
20-Lead Standard Small Outline Package [SOIC] Wide Body (RW-20)
Dimensions shown in millimeters and (inches)
13.00 (0.5118) 12.60 (0.4961)
20
11
7.60 (0.2992) 7.40 (0.2913)
1 10
10.65 (0.4193) 10.00 (0.3937)
0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500) BSC
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
45
COPLANARITY 0.10
8 0 0.51 (0.0201) SEATING 0.32 (0.0126) PLANE 0.33 (0.0130) 0.23 (0.0091)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20A)
Dimensions shown in inches and (millimeters)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
19 18
0.048 (1.21) 0.042 (1.07)
3
0.20 (0.51) MIN 0.021 (0.53) 0.013 (0.33)
0.020 (0.50) R
0.048 (1.21) 0.042 (1.07)
4
TOP VIEW
(PINS DOWN) 8 14 9 13
0.050 (1.27) BSC
0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) 0.120 (3.04) 0.090 (2.29)
BOTTOM VIEW
(PINS UP)
0.020 (0.50) R
0.356 (9.04) 0.350 (8.89) SQ 0.395 (10.02) SQ 0.385 (9.78)
COMPLIANT TO JEDEC STANDARDS MO-047AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-14-
REV. C
AD7226 Revision History
Location 3/03--Data Sheet changed from REV. B to REV. C. Page
Title Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3/03--Data Sheet changed from REV. A to REV. B.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to SPECIFICATIONS RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OUTLINE DIMENSIONS updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 RS-20 package added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Updated RS-20 package OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REV. C
-15-
-16-
C00987-0-3/03(C)
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